Applications on Advanced Architecture Computers [appl math] by G. Astfalk

By G. Astfalk

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2 33 CACHE MEMORY PRINCIPLES If CPU registers are considered the peak of the memory performance hierarchy, then cache memory is the second tier. In contrast to registers, cache memory is designed to be an automatically allocated resource controlled by hardware; its existence is, to a large degree, invisible to the executing program. The theory of operation of cache memory is that a special hardware controller can automatically exploit the locality inherent in program and datamemory accesses. It does this by retaining the most recent words of data accessed by the processor in a special high-speed memory—the cache memory.

Started in June of 1986 and was completed by September. The MIPS chips had two deficiencies: the physical memory space was not contiguous, and the existing Unix kernel software did not conform to hardware word-alignment-addressing constraints. Resolving both of these problems required modifications to the Unix kernel. Each time the operating system was ported to new hardware (which was done three times to different hardware revisions before first customer shipment), a period of approximately six weeks of intense debugging was required to identify new problems.

1. 37 T h e cache coherency problem. As a simple example o f a cache coherency problem, consider a locking flag that is kept in an integer variable that is shared among several processes. If the flag is zero, a shared resource is free. I f it is non-zero, then the resource is busy and a process desiring the resource must wait. N o w , if a C P U reads the locking flag variable from memory and finds it to be nonzero, it may use a short loop to continually test the value, waiting for it to become zero (such a loop is called a spin-lock).

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