Algorithmic and Register-Transfer Level Synthesis: The by Donald E. Thomas, Elizabeth D. Lagnese, Robert A. Walker,

By Donald E. Thomas, Elizabeth D. Lagnese, Robert A. Walker, Jayanth V. Rajan, Robert L. Blackburn, John A. Nestor

Recently there was elevated curiosity within the improvement of computer-aided layout courses to help the procedure point dressmaker of built-in circuits extra actively. Such layout instruments carry the promise of elevating the extent of abstraction at which an built-in circuit is designed, hence freeing the present designers from some of the information of common sense and circuit point layout. The promise additional means that a complete new crew of designers in neighboring engineering and technological know-how disciplines, with a long way much less figuring out of built-in circuit layout, can be in a position to elevate their productiveness and the performance of the structures they layout. This promise has been made many times as each one new greater point of computer-aided layout device is brought and has many times fallen in need of achievement. This publication provides the result of study aimed toward introducing but better degrees of layout instruments that would inch the built-in circuit layout neighborhood towards the achievement of that promise. 1. 1. SYNTHESIS OF built-in CmCUITS within the built-in circuit (Ie) layout strategy, a habit that meets definite requisites is conceived for a approach, the habit is used to provide a layout by way of a suite of structural good judgment parts, and those good judgment parts are mapped onto actual devices. The layout procedure is impacted via a suite of constraints in addition to technological details (i. e. the good judgment parts and actual devices used for the design).

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Extra info for Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench

Sample text

An example of SELECT-to-SELECT Transfer is shown in Figure 3-11, where the shaded operator is moved to the corresponding branch in the previous SELECT; if each SELECT will later become a separate pipestage, this moves the shaded operator into an earlier stage.

In the rightmost alternative, the design has been structurally partitioned across two chips, perhaps in response to physical constraints. Note that structural partitioning and behavioral partitioning are not mutually exclusive, as both might be applied to the same design. This chapter describes a set of transformations to support these three design alternatives. Using these transformations, a designer can begin with a single "generic" behavioral description, transform the design to obtain a more efficient control structure, and behaviorally or structurally transform that design to explore further system-level design alternatives, such as concurrency or pipelining.

In the Workbench, CALLs are not expanded if the vtbody being CALLed has more than one LEAVE operator, or if it RESTARTs, RESUMEs, or TERMINATEs itself; these restrictions avoid GOTO-style jumps to the interior of a vtbody (which are not allowed in the VT). An automated version of this transformation is also available, that either expands inline all CALLs to the specified vtbody, or recursively expands inline all CALLS inside the specified vtbody. An example of the latter is shown in Figure 3-2, where all CALLs in vtbody Vi:A are recursively expanded inline; the resulting VT is shown on the right side of the figure.

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