A SystemC Primer by J. Bhasker

By J. Bhasker

*** SOFTCOVER variation (with no CD) OF ebook is obtainable! ISBN 978-0-9846292-0-6 (Hardcover version is not any longer to be had) *** it is a beginner's booklet on SystemC particular for either approach designers in addition to good judgment designers. Designers who already be aware of VHDL or Verilog HDL will locate the e-book really easy to learn and know about SystemC. Designers can in a truly short while begin writing SystemC versions and simulating them with the knowledge supplied within the e-book.

An very good foreword has been supplied by way of Stan Krolikoski, the Open SystemC Initiative Chairman -- " ...a primer that gently introduces the reader to the complexities of SystemC via connection with universal electronic layout ideas ..."

The moment version incorporates a CD besides, plus more suitable insurance of the newest SystemC features.

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T h e conflict situation is more complex when multiple vector transfers occur at the same time. Since each processor has 3 m e m o r y ports, a system with two processors can have up to 6 vector transfers in progress at the same time. Several possible conflicts may occur. 4. Memory Conflicts for Vector Operations lO . . 5. 3 i l l u s t r a t i n g t h e b a n k conflicts w h i c h o c c u r w i t h vectors o f s t r i d e 32. CP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 Line 1 2 Bank 3 Second vector element delayed 3 clock cycles Third vector element delayed 3 clock cycles Fourth vector element delayed 3 clock cycles Fifth vector element delayed 3 clock cycles I = first element, 2 = second element, etc.

4. The S's indicate the functional unit setup time, while the H's indicate a delay caused by a functional unit waiting for the first chained output result to become available. The group of instructions completes at clock cycle 33. If no chaining occurred, this group of instructions would complete execution at clock cycle 46. IO 20 30 ...... 5. ing. 4 illustrating v e c t o r chain- Chaining is transparent to the user. T h a t is, it is either done or not done as appropriate without specification by the programmer.

There are no direct connections between the shared registers and the functional units. The shared address register values may be moved to or from the A registers. Similarly, the shared scalar registers may be moved to or from the S registers. 7. 1. These registers are connected to the functional units and there are several operations which can be performed directly on these registers. The test-and-set instruction (0034) tests the value of a semaphore register. If the semaphore value is 0, the test-and-set instruction issues and the register is set to 1.

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