A Designer’s Guide to Built-In Self-Test by Charles E. Stroud

By Charles E. Stroud

A fresh technological develop is the paintings of designing circuits to check themselves, known as a integrated Self-Test (BIST). this concept was once first proposed round 1980 and has grown to turn into the most vital checking out strategies on the present time, in addition to for the longer term. This e-book is written from a designer's viewpoint and describes the key BIST methods which have been proposed and applied due to the fact that 1980, besides their merits and obstacles. The BIST methods contain the integrated good judgment Block Observer, pseudo-exhaustive BIST strategies, round BIST, scan-based BIST, BIST for normal buildings, BIST for FPGAs and CPLDs, mixed-signal BIST, and the combination of BIST with concurrent fault detection ideas for online checking out. specific realization is paid to system-level use of BIST with a view to maximize the advantages of BIST via diminished trying out time and value in addition to excessive diagnostic solution. the writer spent 15 years as a dressmaker at Bell Labs the place he designed over 20 construction VLSI units and three creation circuit forums. 16 of the VLSI units contained BIST of varied varieties for normal buildings and normal sequential common sense, together with the 1st BIST for Random entry stories (RAMs), the 1st thoroughly self-testing built-in circuit, and the 1st BIST for mixed-signal structures at Bell Labs. He has spent the prior 10 years in academia the place his study and improvement maintains to target BIST, together with the 1st BIST for FPGAs and CPLDs besides persevered paintings within the quarter of BIST for basic sequential common sense and mixed-signal structures. He holds 10 US patents (with five extra pending) for varied forms of BIST ways. consequently, the writer brings a special combination of information and event to this functional advisor for designers, try out engineers, product engineers, approach diagnosticians, and managers.

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Since an open in a wire prevents the propagation of a signal past the open, inputs to gates and transistors on the other side of the open will remain constant, creating behavior equivalent to the gate-level and transistor-level fault models. As a result, opens can be detected by test vectors for either gate-level or transistor-level fault models. Therefore, only shorts between wires are of interest and they are more commonly referred to as bridging faults. 5a denoted A and B at the signal source end of the wires and A´ and B´ at the signal destination end of the wires with a resistive short between the two wires.

4. In order to detect the A NFET stuck-off, the ‘00’ test vector (ordered for AB) must first be applied to get a logic 1 at the output of the gate. Next, the ‘10’ test pattern must be applied to detect the fault such that the faulty circuit will continue to produce a logic 1 while the faultfree circuit will produce a logic 0. Similarly, to detect the B NFET stuck-off, the ‘00’ test vector must first be applied to get a logic 1 at the output of the gate, followed by the ‘01’ test vector so that the faulty “storage state” is detected.

Alternative approaches include computer-aided design (CAD) based techniques such as formal verification or automatic test pattern generation (ATPG) based methods [63]. A “faulty” circuit in this case would indicate that there is either a design error or a problem with the design verification vectors that prevented manipulation of the circuit in the way the designer had originally intended. A “good” circuit, on the other hand, does not mean that the design is free of errors. This requires sufficient design verification be performed to obtain a high level of confidence that the design is errorfree (or at least that there is a relatively low probability of any remaining design error).

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